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Guild: wafer.space Community
Channel: ℹ️ - Information / ⁉️-questions / Splitting the pad ring for a 5 V eFuse segment on a 1x0p5 slot. OK for precheck?
After: 2026-08-31 11:59 p.m.
Before: 2026-10-01 12:00 a.m.
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[2026-09-26 7:26 p.m.] sriharshapy
Hi all. I'm designing a half-height (1x0p5) chip for Run 3 with the 3.3 V core (as_sc_mcu7t3v3 + ocd_io). It uses two eFuse macros from Egor's compiler. Egor's Run 1 report says writes are only reliable at 5 V (~15 mA/bit), while reads work at 3.3 V. So I'd like to give the eFuses their own supply segment:
- Two `gf180mcu_ocd_io__brk5` cells on the west side isolate the last six pads: analog 3..0, DVSS 6 and DVDD 6.
- DVDD 6 goes to the eFuse voltage (<= 5.0 V while programming), and analog 0 carries VDD_EFUSE into the core.
- No template power/ground pad is removed or moved. Only DVDD 6's voltage and the two break cells change. VSS stays continuous, since brk5 only carries VSS.

Questions:
1. Will precheck accept a pad ring modified this way (break cells, one DVDD pad at a different voltage)? Is there any rule on a minimum number of DVDD/DVSS pads per segment?
2. On the Run 1 1x0p5 CoB board, DVDD 6 (bond pad 61) is on its own net `PWR_AUX_1`, and analog 0 (pad 63) is separate too. Will the Run 3 half-slot carrier keep that arrangement?
3. Leo, I noticed you added eFuses to one of your 3.3 V designs and then took them out about two weeks later. Was that for a supply, DRC/precheck or area reason? Anything I should watch out for?

I've also emailed info@wafer.space with the board-voltage part of this, and asked Egor about 3.3 V operation on the compiler's GitHub (egorxe/gf180_efuse_compiler#1). Posting here too in case the answers help others. Thanks!

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[2026-09-27 12:08 a.m.] mithro_
@Egor Lukyanchenko - Maybe you know?


[2026-09-27 3:58 a.m.] egorxe
Hi! These questions are more targeted towards @Leo Moser (mole99) and @Andrew Wingate, but I'll try to answer to the best of my knowledge.
1. The precheck should pass without problems I think.
2. I hope that will be kept as it makes sense.
3. We had a discussion with Leo about that. Experiments with the Run 1 testchip have shown that 3.3V is not enough to blow the fuses, so he decided to drop it.


[2026-09-27 7:52 a.m.] rebelmike
For 2, the intention is to keep each power supply separate on the CoB board, only the grounds are connected together.


[2026-09-27 8:22 a.m.] mole99
Hi @heathcliff,

1. Yes, the precheck should pass. The `Pad` layer (pad opening) is checked against a golden reference (first AND and then XOR) to ensure that the bonding machine has something to bond to. Which circuit is connected to the bond pad is entirely up to you.

2. We didn't plan on any functional changes to the CoB, but Andrew can confirm that for sure. As Mike mentioned, only the grounds are shorted together.

3. Yes, the reason is as Egor mentioned: 3.3V is not enough to blow the fuses, so I dropped the eFuses for this FPGA version, as I wanted to target 3.3V-only. In a future version, I would also like to have multiple power domains in the core and add the eFuses back.

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[2026-09-27 11:22 a.m.] egorxe
@heathcliff  I've answered your questions in the GH issue. @Leo Moser (mole99) As a side note, it would be very useful for the analog and mixed designs to have two separate voltages. Maybe something like the approach took by heathcliff could be optionally introduced into the template? The other option is probably modifying the IO library to separate VDD & DVDD and adding pad variants for both, but that looks like much more work.


[2026-09-27 11:57 a.m.] 246tnt
I'm planning on making an analog pad that allows analog voltage input higher than VIO, exactly so you can feed voltage inside without needing to have the VIO be 5V or break the ring.

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[2026-09-27 11:58 a.m.] 246tnt
We have an io library with separate VDD and DVDD already btw.


[2026-09-27 12:50 p.m.] egorxe
> I'm planning on making an analog pad that allows analog voltage input higher than VIO, exactly so you can feed voltage inside without needing to have the VIO be 5V or break the ring.

@tnt Cool, thanks! Will it be something like the current analog pad but without the ESD clamps or something more complex?

> We have an io library with separate VDD and DVDD already btw.

You mean the ocd_io where core & IO voltage are separated, right? I've actually meant not this, but having two independent core voltage rails within the pad ring and for example clamping the digital pads to one of them and analog to another. That would allow using different supplies for the digital and analog domain if needed without breaking the ring, but requires a lot of work obviously.


[2026-09-27 12:59 p.m.] 246tnt
Well, with ESD clamp, but only referenced to GND.
So a diode for negative events and a GGNMOS for positive events ( should be ok up to 8V or so ).

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[2026-09-27 6:20 p.m.] sriharshapy
Thanks everyone, this really helped!


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